The contributions of EMCMCC towards research and developments.


In-situ EMC testing using surface current sense wires

ABSTRACT: In-situ EMC testing is, for large fixed systems and installations within the scope of the European EMC Directive, not a primary requirement other than unintended RF emissions may not affect intended radio frequency communication services, like the requirements of IEC/EN 55011 outside the end-user's premises. Whatever happens on the premises of the industrial end-user is a matter of negotiations and agreements between the various system suppliers and the end-user, in particular when EMC is lacking between two or more (sub-) systems installed. A formal standardized method for verification is IEC CISPR/TR 16-2-5 Ed. 1.0, but one of the root problems is the usage of common EMC measurement antenna nearby a conductive object, when performing in-situ EMC investigations, which remains doubtful. In a pan-European TEMCA-2 (ended 2007) project several investigations have been carried out which have not (yet) resulted in a standardized test method but their results have been reported at several international symposia. In this paper, part of an adapted in-situ measurement approach is presented which minimizes the interaction with the local EM-environment even further by using surface current sense wires. This new test method has already been submitted as NP to the international standardization bodies concerned.

Noise reduction in nanometre CMOS

ABSTRACT: With nanometre scaling, the amount of transistors per 100 square millimetre will increase following Moore's Law. The maximum power will, without additional cooling, be limited to a few watt whereas the on- and off-chip clock and data speeds will increase further. To accommodate this, the core supply voltages are reduced further down to below 1 volt as where the peripheral supply voltages will have to follow international agreed voltages levels to enable interfacing. While lowering the core supply voltages, the on-chip noise margin will drop accordingly and tight on- and off-chip decoupling measures are necessary. However by application, RF switching noise from nanometre CMOS designs are forced out of their packages through the supply and ground pins when applying conventional off-chip decoupling is applied. In this paper, the state-of-the-art, as well as a new noise reduction technique, which is possible with today's nanometre CMOS processes, will be discussed together with guidance to accompanying complementary off-chip measures.

Discrete spread-spectrum sampling (DSSS) to reduce RF emission and beat frequency issues

ABSTRACT: Using spread spectrum clocking techniques with digital systems is quite commonly used to reduce RF emission at the higher harmonics, this to fulfill the existing EMC regulations. Results have been reported frequently. However, with analogue interfaces, fixed frequency sampling is still in place for the sake of signal reconstruction and processing algorithms. In this paper the use of discrete spread spectrum sampling is introduced which will not only reduce the RF emission from these analogue-to-digital or digital-to-analog interfaces but will also eliminate the effect of beat frequencies. The beat frequency signal resulting from fixed frequency sampling harmonics and fixed frequency RF interference, will be spread out as sideband noise in the baseband of the intended signal. A similar DSS technique has been introduced in a patented ABCD power conversion concept using 16 (24) fixed frequencies selected randomly.

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

ABSTRACT: Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to today's billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

Impulse immunity test method for digital integrated circuits

A methodology is presented to test susceptibility of digital ICs for impulsive phenomenon. This paper gives an explanation of the impulse immunity test strategy and the test methods developed. Some results will be discussed.

Design of experiments on an EMC test chip for the interrogation of SI and EMC measures

ABSTRACT: Many IC design houses, manufacturers and silicon foundries give SI and EMC rules and guidelines but the possible interaction between the various measures is mostly unknown. An EMC test-chip has been developed with the aim to evaluate the presently known EMC design rules and to investigate some new measures like power grid adjustments and dampening resistances between peripheral supply and substrate. Instead of carrying out an experiment permuting one factor at a time (OFAT) a multi-parameter analysis technique, using design-of-experiments (DOE) was created with ultimately positive results. The experiment has been carried out with 8 core and 5 peripheral parameter settings considering 7 responses: means 7(38+35)=47628 relations. This first EMC test-chip has been designed in C075 (CMOS035) technology, as with the start of this project the proper RF device modelling was available. The evaluation results of the EMC test-chip are included in the on-chip EMC design rules for C075 and newer process technologies

Modeling and analysis of the return path discontinuity caused by vias using the 3-conductor model

ABSTRACT: Parasitics associated with the current return path discontinuity (RPD) are among the major factors affecting the signal integrity (SI) and electromagnetic compatibility (EMC) behavior of digital circuits with fast switching drivers. Vias that connect signal lines referenced to different planes cause RPD, such that the signal return current has to jump between the planes to close the current loop. In addition to the plane-vias (for planes at the same voltage level) and decoupling capacitors (for planes at different voltage levels) between the planes, the inter-plane capacitance represents a possible return path, which has to be modeled as a distributed element for plane dimensions comparable to a wavelength.

Vectorial voltage measurement for ICs on multi-IC PWB

ABSTRACT: When a multi-IC PWB fails compliance with the EMC emission requirements it is necessary to locate the IC(s) that can be the cause for this shortcoming. With many applications, too high-induced voltage levels in the ground layer of the PWB are the main cause the RF emission. Many measurement tools do exist to measure the nearfield magnetic field component underneath a PWB. These tools are sensitive enough to locate RF emission areas when measured in the frequency domain but are not fine enough to allocate a certain quadrant of an IC. Most certainly not when the emission is dependent on time i.e. instruction codes being processed. For this purpose, a measurement methodology in the time domain, containing amplitude and phase information has been developed. Uptill recent this has not been feasible by lacking suitable measurement equipment. In this paper a measurement technique is defined in the time domain with sufficient sensitivity and with the capability to be synchronised with the clock frequency or other trigger events generated by the system to be measured.

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