ESDA-IEW: "Bridging the gap between IC design and its application"

IC ESD protection measures need to combine the handling constraints effectively without causing any functional drawback to its foreseen application. With today's nanometer processes, the vulnerability of the circuits to be protected increases though on the opposite side the RF immunity requirements are enhanced for the so called 'global' pins at the application level. Questions need to be answered on what can and has to be done at the application, in the package and on-silicon to close this gap efficiently while being able to demonstrate compliance to the ESD standards applicable at the various verification levels concerned.More information

APEMC2012

A contribution will be given on the development of measurement methods to be used at the intermediate level, being the assembled PCBs. These small, even up to larger PCBs used in 19-inch racks need to be qualified prior to release and/or integration into a larger system. A chain of measurement methods is set which can be used from the IC level up to the system qualification level.

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APEMC2012

A point of concern, which will be covered, is the fact that still most ICs, which already have on-chip EMC improvement measures are falsely applied at the PCB level and no 'fast & simple' feedback measurement methods exist.

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APEMC2012

An RF emission test method is under development which can identify to action which is going on on-chip. This will be a collaboration of efforts earlier used with the IEC 62215-2 test method used to determined impulse immunity analysis. The RF emission method is still in progress, for the first topic, the first evidence is in place.

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Workshop High-end IC decoupling strategies

Many IC suppliers, in particular for FPGA, micro-controllers and processors provide their customers with IC decoupling strategies using a sea of capacitors where the PCB area involved might result in 3 to 4 times the area needed for the placement of the IC itself. The origin of this approach is highlighted and alternative solutions are presented which decimate the number of capacitors needed. Accordingly, the multiple resonances which may occur on the PCB will decimate to; typically noise reduction of 20 – 30 dB is achieved.

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NEW: ‘Electromagnetic Compatibility' by Mart Coenen

"The book is of great interest for designers and engineers in industry and could be a basis with corporate trainings. It is also useful as basic material for high school and universities. The book has been updated and gives a practical overview of most electromagnetic compatibility issues with many useful examples for those involved with design and installations"

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Call for papers closed!!

May 30, 2011 was the last day that papers could be submitted to EMCompo2011. EMCCompo has already proven its status when it concerns EMC developments w.r.t. ICs. The event in Dubrovnik , Nov 6 to 9, 2011, will provide interesting key-notes , novel PhD exchanges as well as distinguished lectures.

See www.emccompo2011.org

Bits & chips Hardware conference; June 9th 2011

www.hardwareconference.nl/EMCMCC has the contribution: Meeting the (EMC) IC requirements means knowing these demands.

EMC requirements and test methods should be cascadable to enable EMC testing along the development chain. Existing requirements have never be developed with this intend in mind leading to lots of frustration during system integration processes as one can't rely on the compliance indicated.